Computer Architecture - Study Mode
[#421] The RAS and CAS signals are provided by the . . . . . . . .
Correct Answer
(C) Memory controller
[#422] . . . . . . . . is used to detect and correct the errors that may occur during data transfers.
Correct Answer
(A) ECC
[#423] The less space consideration as lead to the development of . . . . . . . . (for large memories).
Correct Answer
(D) Both SIMM's and DIMS's
[#424] MRDC stands for . . . . . . . .
Correct Answer
(B) Memory Ready Command
[#425] . . . . . . . . register Connected to the Processor bus is a single-way transfer capable.
Correct Answer
(D) Z