Computer Architecture - Study Mode
[#96] The mode of transmission of data, where one bit is sent for each clock cycle is . . . . . . . .
Correct Answer
(D) Isochronous
[#97] What does the hardwired control generator consist of?
Correct Answer
(D) All of the mentioned
[#98] If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation).
Correct Answer
(C) ~1
[#99] A narrow SCSI BUS has . . . . . . . . data lines.
Correct Answer
(B) 8
[#100] The difference between DRAM's and SDRAM's is/are . . . . . . . .
Correct Answer
(B) The SDRAM's make use of clock